// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.4.0.70
// Netlist written on Wed Dec 24 11:23:22 2014
//
// Verilog Description of module ip_gddr71tx
//

module ip_gddr71tx (clkout, ready, refclk, sclk, start, sync_clk, 
            sync_reset, data0, data1, data2, data3, dout) /* synthesis syn_noprune=1, NGD_DRC_MASK=1, syn_module_defined=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(215[8:19])
    output clkout;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(225[17:23])
    output ready;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    input refclk;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(217[16:22])
    output sclk;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(227[17:21])
    input start;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(218[16:21])
    input sync_clk;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(219[16:24])
    input sync_reset;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(220[16:26])
    input [6:0]data0;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(221[22:27])
    input [6:0]data1;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(222[22:27])
    input [6:0]data2;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(223[22:27])
    input [6:0]data3;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(224[22:27])
    output [3:0]dout;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(228[23:27])
    
    wire sync_clk /* synthesis SET_AS_NETWORK=sync_clk */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(219[16:24])
    wire sclk /* synthesis SET_AS_NETWORK=sclk */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(227[17:21])
    wire n779 /* synthesis nomerge= */ ;
    
    wire buf_clkout, preamble1, scuba_vhi, buf_douto3, buf_douto2, 
        buf_douto1, buf_douto0, reset, eclko;
    wire [2:0]cs_gddr_sync;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    
    wire GND_net;
    
    OB Inst7_OB (.I(buf_clkout), .O(clkout)) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(278[8:45])
    ODDR71B Inst5_ODDR71B3 (.D0(data3[0]), .D1(data3[1]), .D2(data3[2]), 
            .D3(data3[3]), .D4(data3[4]), .D5(data3[5]), .D6(data3[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto3)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B3.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B2 (.D0(data2[0]), .D1(data2[1]), .D2(data2[2]), 
            .D3(data2[3]), .D4(data2[4]), .D5(data2[5]), .D6(data2[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto2)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B2.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B1 (.D0(data1[0]), .D1(data1[1]), .D2(data1[2]), 
            .D3(data1[3]), .D4(data1[4]), .D5(data1[5]), .D6(data1[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto1)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B1.GSR = "ENABLED";
    ODDR71B Inst5_ODDR71B0 (.D0(data0[0]), .D1(data0[1]), .D2(data0[2]), 
            .D3(data0[3]), .D4(data0[4]), .D5(data0[5]), .D6(data0[6]), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_douto0)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst5_ODDR71B0.GSR = "ENABLED";
    VHI scuba_vhi_inst (.Z(scuba_vhi));
    FD1S3DX Inst4_FD1S3DX (.D(scuba_vhi), .CK(sclk), .CD(reset), .Q(preamble1)) /* synthesis syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(303[13:82])
    defparam Inst4_FD1S3DX.GSR = "ENABLED";
    OB Inst3_OB3 (.I(buf_douto3), .O(dout[3])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(305[8:47])
    CLKDIVF Inst2_CLKDIVF (.CLKI(eclko), .RST(reset), .ALIGNWD(GND_net), 
            .CDIVX(sclk)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst2_CLKDIVF.GSR = "DISABLED";
    defparam Inst2_CLKDIVF.DIV = "3.5";
    ECLKSYNCB Inst1_ECLKSYNCB (.ECLKI(refclk), .STOP(cs_gddr_sync[0]), .ECLKO(eclko)) /* synthesis syn_instantiated=1 */ ;
    ODDR71B Inst6_ODDR71B (.D0(preamble1), .D1(preamble1), .D2(GND_net), 
            .D3(GND_net), .D4(GND_net), .D5(scuba_vhi), .D6(scuba_vhi), 
            .ECLK(eclko), .SCLK(sclk), .RST(reset), .Q(buf_clkout)) /* synthesis syn_instantiated=1 */ ;
    defparam Inst6_ODDR71B.GSR = "ENABLED";
    OB Inst3_OB2 (.I(buf_douto2), .O(dout[2])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(308[8:47])
    OB Inst3_OB1 (.I(buf_douto1), .O(dout[1])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(311[8:47])
    OB Inst3_OB0 (.I(buf_douto0), .O(dout[0])) /* synthesis IO_TYPE="LVDS", syn_instantiated=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(314[8:47])
    GSR GSR_INST (.GSR(scuba_vhi));
    PUR PUR_INST (.PUR(scuba_vhi));
    defparam PUR_INST.RST_PULSE = 1;
    VLO i4 (.Z(GND_net));
    LUT4 m0_lut (.Z(n779)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
    defparam m0_lut.init = 16'h0000;
    ip_gddr71txgddr_sync Inst_gddr_sync (.cs_gddr_sync({Open_0, Open_1, 
            cs_gddr_sync[0]}), .ready(ready), .sync_clk(sync_clk), .sync_reset(sync_reset), 
            .n779(n779), .start(start), .reset(reset)) /* synthesis syn_module_defined=1 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(275[26] 276[70])
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module ip_gddr71txgddr_sync
//

module ip_gddr71txgddr_sync (cs_gddr_sync, ready, sync_clk, sync_reset, 
            n779, start, reset) /* synthesis syn_module_defined=1 */ ;
    output [2:0]cs_gddr_sync;
    output ready;
    input sync_clk;
    input sync_reset;
    input n779;
    input start;
    output reset;
    
    wire sync_clk /* synthesis SET_AS_NETWORK=sync_clk */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(219[16:24])
    wire n779 /* synthesis nomerge= */ ;
    wire [2:0]cs_gddr_sync_c;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    
    wire reset_flag, n736;
    wire [3:0]ctrl_cnt;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(77[13:21])
    
    wire n740, n117, n656, n120, n737;
    wire [3:0]n15;
    
    wire n251, n738, n109, n95, n134, n18, ddr_reset_d, n36, 
        n739, n649, n735, n262, n726;
    wire [2:0]stop_assert;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(78[13:24])
    
    wire n35;
    wire [2:0]n1;
    
    wire n653, n6, n10, n609, n417, n725;
    
    LUT4 i1_2_lut_rep_6_3_lut_4_lut (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), 
         .C(reset_flag), .D(ready), .Z(n736)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    defparam i1_2_lut_rep_6_3_lut_4_lut.init = 16'hfffe;
    LUT4 i2_3_lut_rep_10 (.A(ctrl_cnt[3]), .B(ctrl_cnt[2]), .C(ctrl_cnt[1]), 
         .Z(n740)) /* synthesis lut_function=(A+(B+!(C))) */ ;
    defparam i2_3_lut_rep_10.init = 16'hefef;
    LUT4 i614_3_lut (.A(cs_gddr_sync_c[1]), .B(ready), .C(cs_gddr_sync[0]), 
         .Z(n117)) /* synthesis lut_function=(!(A+(B (C)))) */ ;
    defparam i614_3_lut.init = 16'h1515;
    LUT4 i1_2_lut_4_lut (.A(ctrl_cnt[3]), .B(ctrl_cnt[2]), .C(ctrl_cnt[1]), 
         .D(ctrl_cnt[0]), .Z(n656)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i1_2_lut_4_lut.init = 16'h1000;
    LUT4 i1_2_lut_4_lut_adj_1 (.A(ctrl_cnt[3]), .B(ctrl_cnt[2]), .C(ctrl_cnt[1]), 
         .D(ctrl_cnt[0]), .Z(n120)) /* synthesis lut_function=(A+(B+!(C (D)))) */ ;
    defparam i1_2_lut_4_lut_adj_1.init = 16'hefff;
    LUT4 i146_3_lut_4_lut (.A(reset_flag), .B(n737), .C(ctrl_cnt[0]), 
         .D(ctrl_cnt[1]), .Z(n15[1])) /* synthesis lut_function=(!(A (C (D)+!C !(D))+!A ((C (D)+!C !(D))+!B))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    defparam i146_3_lut_4_lut.init = 16'h0ee0;
    FD1S3DX ctrl_cnt__i0 (.D(n15[0]), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[0])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam ctrl_cnt__i0.GSR = "ENABLED";
    LUT4 i144_3_lut_4_lut (.A(reset_flag), .B(n737), .C(ctrl_cnt[0]), 
         .D(ctrl_cnt[3]), .Z(n15[0])) /* synthesis lut_function=(A (C (D)+!C !(D))+!A (B (C (D)+!C !(D)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    defparam i144_3_lut_4_lut.init = 16'he00e;
    FD1P3DX ctrl_cnt__i3 (.D(n15[3]), .SP(n251), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[3])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam ctrl_cnt__i3.GSR = "ENABLED";
    LUT4 i611_2_lut_3_lut_4_lut (.A(ready), .B(n738), .C(ctrl_cnt[3]), 
         .D(reset_flag), .Z(n251)) /* synthesis lut_function=(!(A (C)+!A (B (C)+!B (C (D))))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    defparam i611_2_lut_3_lut_4_lut.init = 16'h0f1f;
    LUT4 i1_2_lut_rep_7_3_lut (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), 
         .C(ready), .Z(n737)) /* synthesis lut_function=(A+(B+(C))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    defparam i1_2_lut_rep_7_3_lut.init = 16'hfefe;
    PFUMX i255 (.BLUT(n109), .ALUT(n95), .C0(ready), .Z(n134));
    FD1P3DX ctrl_cnt__i2 (.D(n18), .SP(n251), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[2])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam ctrl_cnt__i2.GSR = "ENABLED";
    FD1S3BX ddr_reset_d_67 (.D(n779), .CK(sync_clk), .PD(sync_reset), 
            .Q(ddr_reset_d)) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam ddr_reset_d_67.GSR = "ENABLED";
    FD1S3DX reset_flag_65 (.D(n134), .CK(sync_clk), .CD(sync_reset), .Q(reset_flag));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam reset_flag_65.GSR = "ENABLED";
    FD1P3DX ctrl_cnt__i1 (.D(n15[1]), .SP(n251), .CK(sync_clk), .CD(sync_reset), 
            .Q(ctrl_cnt[1])) /* synthesis LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam ctrl_cnt__i1.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_8 (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), .Z(n738)) /* synthesis lut_function=(A+(B)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    defparam i1_2_lut_rep_8.init = 16'heeee;
    LUT4 i608_4_lut (.A(n738), .B(n36), .C(reset_flag), .D(ready), .Z(n18)) /* synthesis lut_function=(!(A (B)+!A (B+!(C+(D))))) */ ;
    defparam i608_4_lut.init = 16'h3332;
    LUT4 i34_4_lut (.A(ctrl_cnt[3]), .B(n739), .C(ctrl_cnt[2]), .D(n737), 
         .Z(n36)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B (C+(D))+!B !(C))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    defparam i34_4_lut.init = 16'hc7c3;
    LUT4 reset_flag_bdd_4_lut_669 (.A(reset_flag), .B(n120), .C(n649), 
         .D(cs_gddr_sync[0]), .Z(n735)) /* synthesis lut_function=(A (B (C+(D))+!B !((D)+!C))+!A (C+(D))) */ ;
    defparam reset_flag_bdd_4_lut_669.init = 16'hddf0;
    FD1P3DX cs_gddr_sync_i1 (.D(n726), .SP(n262), .CK(sync_clk), .CD(sync_reset), 
            .Q(cs_gddr_sync_c[1])) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam cs_gddr_sync_i1.GSR = "ENABLED";
    FD1P3DX stop_assert_60__i2 (.D(n1[2]), .SP(n35), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop_assert[2]));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(123[22:37])
    defparam stop_assert_60__i2.GSR = "ENABLED";
    FD1P3DX cs_gddr_sync_i2 (.D(n653), .SP(n262), .CK(sync_clk), .CD(sync_reset), 
            .Q(ready)) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam cs_gddr_sync_i2.GSR = "ENABLED";
    FD1P3DX stop_assert_60__i1 (.D(n1[1]), .SP(n35), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop_assert[1]));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(123[22:37])
    defparam stop_assert_60__i1.GSR = "ENABLED";
    LUT4 i1_4_lut (.A(ready), .B(ctrl_cnt[3]), .C(n6), .D(reset_flag), 
         .Z(n10)) /* synthesis lut_function=(A+!(B+!(C (D)))) */ ;
    defparam i1_4_lut.init = 16'hbaaa;
    FD1P3DX cs_gddr_sync_i0 (.D(n609), .SP(n117), .CK(sync_clk), .CD(sync_reset), 
            .Q(cs_gddr_sync[0])) /* synthesis syn_preserve=1, LSE_LINE_FILE_ID=5, LSE_LCOL=26, LSE_RCOL=70, LSE_LLINE=275, LSE_RLINE=276 */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam cs_gddr_sync_i0.GSR = "ENABLED";
    LUT4 i522_1_lut (.A(stop_assert[0]), .Z(n1[0])) /* synthesis lut_function=(!(A)) */ ;
    defparam i522_1_lut.init = 16'h5555;
    FD1P3DX stop_assert_60__i0 (.D(n1[0]), .SP(n35), .CK(sync_clk), .CD(sync_reset), 
            .Q(stop_assert[0]));   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(123[22:37])
    defparam stop_assert_60__i0.GSR = "ENABLED";
    LUT4 i1_3_lut_4_lut (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), .C(reset_flag), 
         .D(start), .Z(n95)) /* synthesis lut_function=(A (C)+!A (B (C)+!B (C (D)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    defparam i1_3_lut_4_lut.init = 16'hf0e0;
    LUT4 i2_3_lut (.A(reset_flag), .B(stop_assert[2]), .C(start), .Z(n35)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    defparam i2_3_lut.init = 16'h1010;
    LUT4 i354_2_lut (.A(ctrl_cnt[2]), .B(ctrl_cnt[0]), .Z(n417)) /* synthesis lut_function=(A (B)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(77[13:21])
    defparam i354_2_lut.init = 16'h8888;
    LUT4 i524_2_lut (.A(stop_assert[1]), .B(stop_assert[0]), .Z(n1[1])) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;
    defparam i524_2_lut.init = 16'h6666;
    LUT4 i2_3_lut_adj_2 (.A(cs_gddr_sync_c[1]), .B(n735), .C(ready), .Z(n609)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
    defparam i2_3_lut_adj_2.init = 16'h0404;
    LUT4 i2_2_lut_3_lut (.A(stop_assert[1]), .B(stop_assert[0]), .C(n35), 
         .Z(n649)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_2_lut_3_lut.init = 16'h8080;
    LUT4 i531_2_lut_3_lut (.A(stop_assert[1]), .B(stop_assert[0]), .C(stop_assert[2]), 
         .Z(n1[2])) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;
    defparam i531_2_lut_3_lut.init = 16'h7878;
    LUT4 i1_2_lut (.A(cs_gddr_sync_c[1]), .B(ddr_reset_d), .Z(reset)) /* synthesis lut_function=(A+(B)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i2_4_lut (.A(cs_gddr_sync[0]), .B(cs_gddr_sync_c[1]), .C(n10), 
         .D(start), .Z(n653)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;
    defparam i2_4_lut.init = 16'h1000;
    LUT4 n23_bdd_2_lut_3_lut (.A(cs_gddr_sync[0]), .B(ready), .C(n725), 
         .Z(n726)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam n23_bdd_2_lut_3_lut.init = 16'h2020;
    LUT4 i1_2_lut_3_lut_3_lut (.A(cs_gddr_sync[0]), .B(ready), .C(cs_gddr_sync_c[1]), 
         .Z(n262)) /* synthesis lut_function=(!(A (B)+!A (C))) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(105[3] 137[6])
    defparam i1_2_lut_3_lut_3_lut.init = 16'h2727;
    LUT4 n128_bdd_4_lut (.A(cs_gddr_sync_c[1]), .B(reset_flag), .C(ctrl_cnt[0]), 
         .D(n740), .Z(n725)) /* synthesis lut_function=(A ((D)+!C)+!A !(B+((D)+!C))) */ ;
    defparam n128_bdd_4_lut.init = 16'haa1a;
    LUT4 i599_2_lut_rep_9 (.A(ctrl_cnt[0]), .B(ctrl_cnt[1]), .Z(n739)) /* synthesis lut_function=(A (B)) */ ;
    defparam i599_2_lut_rep_9.init = 16'h8888;
    LUT4 i2_2_lut_3_lut_adj_3 (.A(ctrl_cnt[0]), .B(ctrl_cnt[1]), .C(ctrl_cnt[2]), 
         .Z(n6)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i2_2_lut_3_lut_adj_3.init = 16'h8080;
    LUT4 i1_4_lut_adj_4 (.A(n656), .B(reset_flag), .C(cs_gddr_sync_c[1]), 
         .D(cs_gddr_sync[0]), .Z(n109)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(79[13:25])
    defparam i1_4_lut_adj_4.init = 16'heccc;
    LUT4 i142_4_lut (.A(n736), .B(ctrl_cnt[3]), .C(ctrl_cnt[1]), .D(n417), 
         .Z(n15[3])) /* synthesis lut_function=(!((B (C (D))+!B !(C (D)))+!A)) */ ;   // d:/rd_work_area/new_work_areard1093/rd1093_display_interface/rd1093/source/verilog/ecp5/clarity/ecp5_ip/ip_gddr71tx/ip_gddr71tx.v(226[17:22])
    defparam i142_4_lut.init = 16'h2888;
    
endmodule
